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1. Field of the Invention
The present invention generally relates to voice and data communication systems. More particularly, this invention relates to synchronous wireless communication systems.
2. Description of the Related Technology
T-carrier systems have become an essential part of modern telecommunications systems. A T-carrier system is found in every telephone company in North America. A T-carrier allows for transmission of one or more telephone calls or data connections by modem. The basic unit of signaling is DS0, followed by progressively higher speed signaling rates. First generation T-carrier systems, called T1, which carry Digital Signal Level 1 (DS 1), employ a full duplex all-digital service. The digital stream is capable of carrying standard 64 kilobits per second (kbps) channels in which 24 channels are multiplexed to create an aggregate of 1.536 Mega bits per second (Mbps). Time division multiplexing (TDM) allows a channel to use one of 24 timeslots. More particularly, the 24 channels are time-division multiplexed into a frame to be carried along the data stream line. Typically, each frame contains one sample of 8 bits from each of the channels, and a framing bit. This structure results in a frame having 193 bits. In view of employing pulse code modulation (PCM) on each channel, there are 8000 frames per second. Hence, a frame is 125 microseconds long. Eight kbps of overhead bits are added (due to framing) to 1.536 Mbps, thereby yielding an aggregate of 1.544 Mbps.
A TI system employs Alternate Mark Inversion (AMI) coding to reduce the required bandwidth of 1.5 MHz by a factor of two. The transmission is byte-synchronous whereby timing synchronization for each channel is derived from the pulses that appear within the samples (8 bits in each sample). This timing keeps everything in sequence. Although, a T1 system employs generically 24 channels of 64 kbps data plus 8 kbps of overhead (sometimes referred to as channelized service), the multiplexing equipment may be configured in other ways. For example, T1 may be used for a single channel of 1.536 Mbps, two high-speed data channels at 384 kbps each, and a video channel at 768 kbps. In short, a T1 system service does not have to be channelized into 24 timeslots. It can be split into any number of usable data streams.
T1-systems may multiplex T1 signals into a T2 (DS2) system, but with additional framing bits and 4 times the data rate. This results in an aggregate data rate of 6.312 Mbps. Similarly, a T3 digital link comprises a multiplexing of 7 T2 links (and additional framing bits), resulting in a data rate of 44.736 Mbps. The T3 system has greater demand in high capacity applications. The E carrier services are the European equivalents of the T-carrier.
The problem addressed by the present invention is the special case of transmitting data wirelessly between two systems working at the same nominal frequency. Moreover, the invention is intended for use in high speed data transmission requiring the avoidance of clocks with frequencies higher than the data bit rate.
A common synchronization technique used in the prior art is to synchronize received data to a local clock signal using a D-type flip-flop. This technique, however, produces errors whenever setup and hold time specifications for the flip-flop are violated. Another technique commonly used in the prior art is to use a first-in first-out (FIFO) register to provide the necessary elasticity required to properly synchronize the received data to the local clock signal. The use of a FIFO register, however, results in a certain ripple-through delay and initialization problems associated with such a register. Furthermore, some synchronization techniques are dependent on certain hardware characteristics. One such characteristic is a metastability problem which shows up whenever a flip-flop is clocked without a guaranteed setup and/or hold time, which is exactly what happens when efforts are made to synchronize the data with a new clock.
Text books and papers abound on elastic store implementation. Elastic store read/write pointers can be implemented with separate binary up or down counters, separate up or down ring counters, or single binary up/down or single up/down ring counter. Elastic store data storage implementations include shift registers, addressable latches, and RAM.
Regardless of the implementation, the read and write subsystems are asynchronous to each other and need to be synchronized for some brief time for reliable data transfer. Some sort of arbitration scheme or handshake between read/write clocks, pointers, or data must take place in order to insure that the write data is not changing at the time it is being read (i.e. the metastable condition). Discussion of arbitration logic and its importance to reliable data transmission is neglected in the literature. The impact on Bit Error Rate when arbitration is ignored or improperly implemented is considerable. As an example, consider a 1 micosecond read/write data period and logic with a metastable window of 1 nanosecond. If the read and write are stochastically independent, the probability of reading a bit while it is changing is approximately equal to 1xc3x9710xe2x88x929/1xc3x9710xe2x88x926=1xc3x9710xe2x88x923! In fact the read and write rates are not independent since they are ideally equal. This could result in long periods where the read and write clock drift together, thus producing nearly continuous metastability and catastrophic error rates.
To overcome the above problems, the present invention provides a system and method of buffering data of existing wireless communication systems without the disadvantages of the prior art. The above-mentioned problems are solved by providing an elastic store system which maintains synchronization at the receiver, maintains end-to-end signaling and codes overhead bits needed to encapsulate data frames for wireless communication systems in frequency bands, such as the Industrial, Scientific and Medical (ISM) frequency bands, the National Information Infrastructure (NII), the Personal Communications Services (PCS) and other bands. The ISM frequency bands allocated by the Federal Communications Commission (FCC) are spread across the frequency ranges of 902-928 MHz, 2400-2484 MHz, and 5725-5850 MHz. The NII frequency bands are in the range of 5725-5825 MHz. The PCS technology operates in the frequency range 1850-1910 MHz for the uplink (i.e., mobile transmit, base receive) and 1930-1990 MHz for the downlink (i.e., base transmit, mobile receive). The elastic store system provides full duplex communications while maintaining proper end-to-end signaling schemes for a variety of wireless communication systems, such as mobile systems employing Code Division Multiple Access (CDMA) in which a transmitted signal is spread over a band of frequencies much wider than the minimum bandwidth required to transmit the signal, Time Division Multiple Access (TDMA) where the users share the radio spectrum in the time domain, Frequency Division Multiple Access (FDMA) where a user is allocated at least one unique frequency for communication without interference with users in the same frequency spectrum, or similar technologies.
In accordance with one embodiment of the present invention, the elastic store system provides a means of buffering a data stream to be transmitted in the ISM frequency bands, which may be written into its input at a different rate than it is read from its output. The elastic store system comprises two main subsystems: a transmit elastic store (TxEsto) subsystem at a transmitter and a receive elastic store (RxEsto) subsystem at a receiver. In one direction, the TxEsto generates a stuffing request, and provides underflow and overflow status of the data received from a channelizer to a framer for further processing. After detailed parallel processing, this data is sent over the air interface in the ISM band frequencies to the receiver. At the receiver, the RxEsto subsystem receives data from a deframer. For synchronization between transmitter and receiver clocks, the RxEsto subsystem clocks out the data, which is stripped off the data overhead bits, at the same rate as it was sent before encapsulation at the transmitter.
One embodiment of the present invention is a synchronous elastic store system, comprising a shift register having a plurality of data bits, the shift register receiving a stream of digital input data and a master clock input signal which is independent of the digital input data; and an arbiter that arbitrates between a read request and a write request to the shift register, the arbiter having the master clock as an input signal and providing a control signal to the shift register.
Another embodiment of the present invention is a synchronous digital elastic store system, comprising a shift register receiving a stream of digital input data and a master clock input signal, said master clock signal being independent of the digital input data; an arbiter that arbitrates between a read request and a write request, the arbiter providing a control signal to the shift register and generating at least one counter control signal; an up/down counter receiving the counter control signal from the arbiter and generating selector control signals; and a selector circuit receiving data from the shift register and receiving selector control signals from the up/down counter, said selector circuit selecting one of the shift register bits to be read from the elastic store.
Yet another embodiment of the invention is a method of storing a stream of digital data in a synchronous elastic store having a shift register, the method comprising the steps of receiving a stream of digital data and a master clock signal at the shift register; synchronously arbitrating between a read request and write request to generate an arbitration control signal; and shifting the digital data into the shift register in response to the arbitration control signal and the master clock signal.
Yet another embodiment of the invention is a synchronous elastic store system, comprising a channelizer; a synchronous elastic store having a read/write arbiter, the synchronous elastic store receivably connected to the channelizer; a framer receivably connected to the synchronous elastic store; and a wireless transmitter circuit receivably connected to the framer.
Yet another embodiment of the invention is a synchronous elastic store system, comprising a wireless receiver circuit; a deframer receivably connected to the wireless receiver circuit; a synchronous elastic store having a read/write arbiter, the synchronous elastic store receivably connected to the deframer; a dechannelizer receivably connected to the synchronous elastic store.